Welcome
Welcome to this SystemVerilog tutorial. We're building a memory chip — a synchronous SRAM — from scratch, one lesson at a time. Here's the interface you'll have working by the end of Part 1:
- Part 1 — SystemVerilog Basics: build the full parameterized SRAM in RTL
- Part 2 — SystemVerilog Assertions: formally verify its correctness
- Part 3 — UVM: stress-test it with a complete verification environment
By the end you'll have a chip that's been hand-coded, formally proved, and exhaustively randomized — the same flow used in industry-grade ASIC design.
Hello World
Before we build anything, let's make sure the simulator is working. Open top.sv. The initial block runs once at time 0. Use
$display
to print a message to the log (the syntax is identical to C's printf.)
One tight paragraph on printf/display notation:
For example, you can write
$display("HELLO, %s WORLD", "SRAM");
Hint: Install Claude Chrome Extension to ask follow up questions on the lessons right in your browser. If any lesson can be improved, please send a PR using the edit link below this text!Every SystemVerilog simulation ends when
$finishis called. Without it, the simulator would run forever waiting for events that never come.